Usefull Links:
tristesse.org/DigilentAtlysResources and tristesse.org/20110209.
VDEis '1' for pixel in the active area (display has an active pixels and an offscreen area).
Using MIG with patches found on internet seems to work.
The DDR2 should be a MT47H64M16HR-25E compatible but, on my pcb, it is a MIRA DDR2. I do not see differences between 50Ohm and 150Ohm.
Settings for 400Mhz DDR2:
C3_MEMCLK_PERIOD : integer := 2500; -- 400Mhz... works? C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; C3_NUM_DQ_PINS : integer := 16; C3_MEM_ADDR_WIDTH : integer := 13; C3_MEM_BANKADDR_WIDTH : integer := 3; C3_CLKOUT0_DIVIDE : integer := 1; C3_CLKOUT1_DIVIDE : integer := 1; C3_CLKOUT2_DIVIDE : integer := 16; C3_CLKOUT3_DIVIDE : integer := 8; C3_CLKFBOUT_MULT : integer := 8; C3_DIVCLK_DIVIDE : integer := 1;
Constraints ripped from Digilent examples are:
############################################################################ # Memory Controller 3 # Memory Device: DDR2_SDRAM->MT47H64M16XX-25E # Supported Part Numbers: MT47H64M16HR-25E ########################################################################### MCB_PERFORMANCE = ? ########################################################################### # I/O TERMINATION ########################################################################### NET "mcb3_dram_dq[*]" IN_TERM = NONE; NET "mcb3_dram_dqs" IN_TERM = NONE; NET "mcb3_dram_dqs_n" IN_TERM = NONE; NET "mcb3_dram_udqs" IN_TERM = NONE; NET "mcb3_dram_udqs_n" IN_TERM = NONE; ############################################################################ # I/O STANDARDS ############################################################################ NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II; NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II; NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II; NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II; NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II; NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II; NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II; NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II; NET "rzq3" IOSTANDARD = SSTL18_II; NET "zio3" IOSTANDARD = SSTL18_II; ############################################################################ # MCB 3 # Pin Location Constraints for Clock, Masks, Address, and Controls ############################################################################ # Address (13 bit) NET "mcb3_dram_a[0]" LOC = "J7" ; NET "mcb3_dram_a[10]" LOC = "F4" ; NET "mcb3_dram_a[11]" LOC = "D3" ; NET "mcb3_dram_a[12]" LOC = "G6" ; NET "mcb3_dram_a[1]" LOC = "J6" ; NET "mcb3_dram_a[2]" LOC = "H5" ; NET "mcb3_dram_a[3]" LOC = "L7" ; NET "mcb3_dram_a[4]" LOC = "F3" ; NET "mcb3_dram_a[5]" LOC = "H4" ; NET "mcb3_dram_a[6]" LOC = "H3" ; NET "mcb3_dram_a[7]" LOC = "H6" ; NET "mcb3_dram_a[8]" LOC = "D2" ; NET "mcb3_dram_a[9]" LOC = "D1" ; # Data (16 bit) NET "mcb3_dram_dq[0]" LOC = "L2" ; NET "mcb3_dram_dq[10]" LOC = "N2" ; NET "mcb3_dram_dq[11]" LOC = "N1" ; NET "mcb3_dram_dq[12]" LOC = "T2" ; NET "mcb3_dram_dq[13]" LOC = "T1" ; NET "mcb3_dram_dq[14]" LOC = "U2" ; NET "mcb3_dram_dq[15]" LOC = "U1" ; NET "mcb3_dram_dq[1]" LOC = "L1" ; NET "mcb3_dram_dq[2]" LOC = "K2" ; NET "mcb3_dram_dq[3]" LOC = "K1" ; NET "mcb3_dram_dq[4]" LOC = "H2" ; NET "mcb3_dram_dq[5]" LOC = "H1" ; NET "mcb3_dram_dq[6]" LOC = "J3" ; NET "mcb3_dram_dq[7]" LOC = "J1" ; NET "mcb3_dram_dq[8]" LOC = "M3" ; NET "mcb3_dram_dq[9]" LOC = "M1" ; NET "mcb3_dram_ba[0]" LOC = "F2" ; NET "mcb3_dram_ba[1]" LOC = "F1" ; NET "mcb3_dram_ba[2]" LOC = "E1" ; NET "mcb3_dram_cas_n" LOC = "K5" ; NET "mcb3_dram_ck" LOC = "G3" ; NET "mcb3_dram_ck_n" LOC = "G1" ; NET "mcb3_dram_cke" LOC = "H7" ; NET "mcb3_dram_dm" LOC = "K3" ; NET "mcb3_dram_dqs" LOC = "L4" ; NET "mcb3_dram_dqs_n" LOC = "L3" ; NET "mcb3_dram_odt" LOC = "K6" ; NET "mcb3_dram_ras_n" LOC = "L5" ; NET "mcb3_dram_udm" LOC = "K4" ; NET "mcb3_dram_udqs" LOC = "P2" ; NET "mcb3_dram_udqs_n" LOC = "P1" ; NET "mcb3_dram_we_n" LOC = "E3" ; ################################################################################## #RZQ is required for all MCB designs. Do not move the location # #of this pin for ES devices.For production devices, RZQ can be moved to any # #valid package pin within the MCB bank.For designs using Calibrated Input Termination, # #a 2R resistor should be connected between RZQand ground, where R is the desired# #input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.# ################################################################################## NET "rzq3" LOC = "L6" ; ################################################################################## #ZIO is only required for MCB designs using Calibrated Input Termination.# #ZIO can be moved to any valid package pin (i.e. bonded IO) within the# #MCB bank but must be left as a no-connect (NC) pin.# ################################################################################## NET "zio3" LOC = "C2" ;
UCF constraint:
NET "SER_RXD" LOC = A16 | IOSTANDARD = LVCMOS33; NET "SER_TXD" LOC = B16 | IOSTANDARD = LVCMOS33;
Port declaration:
SER_TXD : out std_logic; SER_RXD : in std_logic;
There are not big trouble under Windows(XP,Vista,Seven). UART protocol is [0][D0][D1][D2][D3][D4][D5][D6][D7][1] at the favorite baudrate (and remeber to keep the TX signal at 1 during reset and idle).
The loopback test
SER_TXD <= SER_RXD;
works fine.
Last Update: 26 OCT 2011
